A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application

An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a divisionfree reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm can achieve 30Mb/s with 23.4mW power consumption. I. INTRODOCTION Turbo code [1], [2] is very attractive for its error-correcting performance near the Shannon limit. Many standards such as 3GPP [3] and IEEE 802.16e [4] adopt turbo codes to enhance error correction for wireless communication. There are several interesting research works on the implementation of turbo code [5], [6]. Compared to other channel coding in the standard previously mentioned, turbo codes has better BER performance gain than LDPC codes [7], [8]. In IEEE 802.16e, convolutional turbo code (CTC) uses double-binary turbo codes [9] to improve error correcting performance and decoding throughput, and it consists 17 modes including HARQ mechanism with block size from 24 to 2400. Fig. 1 illustrates the turbo encoder block diagram which A B A B CTC Interleaver Constituent Encoder Y1/Y2 W1/W2 A B + S1 + S2 + S3 + + Y W Fig. 1. CTC Encoder Block. consists of a constituent encoder of rate 1/3. The encoder produces two additional parity bits (Y1W1/Y2W2) using two information bits (AB/interleaved AB). The trellis diagram can be generated by the constituent encoder. For example, the trellis diagram for state index=3 is constructed in Fig. 2. For convenience, k is defined as time index from 0 to N-1 where N is the block length in this paper. Four branch metrics, which represent four different information symbols, are sent to state Sk, and Sk also sends four branch metrics to other states Sk+1. As a result, radix-4 ACS unit is used to decode the doublebinary trellis diagram. :symbol=00 :symbol=01 :symbol=10 :symbol=11 time index=k